1. Field of the Invention!
The present invention relates to a semiconductor memory device and, more particularly, to gate circuits of MOS transistors for connecting sense amplifier to bit lines in a DRAM.
With increase in high-packing densities of DRAMs, the physical size of memory cells has been made smaller and smaller recently. As the size of a memory cell becomes smaller, the gate length of a transistor used in the memory cell becomes shorter and shorter. For example, it is of the order of 0.9 .mu.m in 4M bit and of the order of 0.5 .mu.m in 16M bit. If the gate length is made short, the withstand voltage of a transistor will inevitably become low. Thus, it is required to lower a voltage applied to memory cells. Also, power dissipation of a memory cell array can be reduced by lowering voltage applied to a memory cell, namely, the magnitude of voltage on a bit line. Thereby, it becomes possible to avoid an increase of power dissipation resulting from an increase of the number of bit lines which are charged or discharged simultaneously with an increase in packing density.
2. Related Art!
The connection between sense amplifiers and bit lines is almost always made through MOS transistors. These MOS transistors have mainly the following three objects.
(1) The first is to insert a resistive component, which is the channel resistance of an MOS transistor, between a sense amplifier and bit lines to form a CR time constant with capacitance associated with the bit lines and to prevent the bit-line capacitance from being imposed on the sense amplifier as a large capacitive load at the time of operation of the sense amplifier. To this end, the MOS transistor has only to remain conductive. That is, it is necessary only that the gate of the transistor be connected to an externally applied supply voltage Vcc.
(2) The second is to control the gate of the transistor by means of clocks so that it can be turned off when the sense amplifier operates and the bit line can be prevented from being imposed on the sense amplifier as a load. In this case, the gate of the transistor is connected not to a power supply directly but to a clock generating circuit. Since clocks control the gate of the transistor in synchronism with RAS clocks, the clock generator, as part of a row peripheral circuit, is powered from a power supply of the row peripheral circuit or an external power supply.
(3) The third is to use the transistor as an array select switch in the case of a shared sense amplifier which is shared among two pairs of bit lines. As a change-over switch the transistor is connected between the sense amplifier and the bit line. A transistor on the side of a cell array to be selected is rendered conductive and the other transistor is rendered nonconductive. The relationship among the conducting transistor, the sense amplifier and the bit line is the same as that in (1).
In any of the above cases, the transistor for connecting the sense amplifier with the bit line is not used as means for determining a voltage to be written into an memory cell but used merely as a array select switch in the case of the shared sense amplifier, a time-constant forming resistance, etc.
FIG. 1 illustrates power distribution in a hypothetical DRAM. The dynamic RAM is composed of a blocked cell array 10, a sense amplifier group 11, a RAS (Row Address Strobe) peripheral circuit 12, a CAS (Column Address Strobe) peripheral circuit 13 and a data output peripheral circuit 14. The peripheral circuit 14 is generally supplied with a supply voltage Vcc of 5V, the peripheral circuits 12 and 13 are supplied with Vcc2 of, for example, 4V that is produced from the Vcc, and the sense amplifier group 11 is supplied with a voltage Vcc1 of, for example, 3.3 V that is produced from the Vcc. MOS transistors Q1, Q2, . . . , Qn, which connect bit lines of the cell array with the sense amplifiers, have their gates connected to the power supply Vcc in this example and thus function as mere resistors.
When the gates of the MOS transistors are connected to Vcc, i.e., an external power supply, a maximum voltage of the bit lines, i.e., a restore voltage to cells becomes Vcc - Vth which is lower than the supply voltage Vcc. The restore voltage thus obtained tracks the supply voltage so that it always becomes the threshold voltage Vth less than the supply voltage Vcc. The restore voltage on the bit line will also vary as the supply voltage varies. Simply connecting a transistor between a bit line and a sense amplifier and connecting its gate to the supply voltage Vcc, which will lower the operating voltage within a memory cell by about 0.7 V, is not useful as means of limiting the operating voltage stable.
Heretofore there are the following two methods for limiting a voltage applied to a memory cell stable.
(1) A voltage (for example, 3.3 V) is produced within a chip from an externally supplied voltage (for example, 5V) and then used as a supply voltage for the entire circuit in the chip. A voltage transform circuit used for this voltage transformation is well designed to produce a voltage which remains steady irrespective of variations in temperature and externally supplied voltage. Thus, even if the structure of a memory cell is made fine, the voltage transform circuit has only to generate a voltage most suitable for the cell. This method is simple in conception. However, with this method, a voltage for cells which require to be made fine rapidly as packing densities improve and a voltage for peripheral circuits which do not affect the size of a chip even if they are not made fine so rapidly cannot be made independent of each other. Thus, the method is not necessarily suited for an optimum design. With a dynamic RAM in which current dissipation varies dynamically, an instantaneous current produced by the operation of part of circuits has an effect on other circuits as noise. Therefore, with the method which supplies all of circuits within a chip with a common voltage produced by lowering an external supply voltage within the chip, it is not easy to render stable a voltage applied to the cell array.
(2) Within a chip a voltage (for example, 4V) is produced from an external supply voltage (for example, 5V) for application to peripheral circuits. At the same time, a separate voltage (for example, 3.3V) produced within the chip is applied to sense amplifiers so as to lower the voltage applied to the cell array which has progressed in miniaturization. FIG. 1 illustrates this example. Vcc1 is set at 3.3 V and Vcc2 is set at 4V. With this method, the sense amplifiers having a great instantaneous current variation and the peripheral circuits can be operated from separate power supplies. Thus, there is an advantage that the sense amplifiers will provide no noise to other circuits. However, with this method which limits the magnitude of a restore voltage on a bit line with the sense amplifier, the lower the voltage becomes, the smaller the driving power of the sense amplifier for driving data buses becomes. This disadvantageously makes long address access times on the side of columns. This disadvantage will be caused in (1) as well when the voltage is lowered.
In the case where, in that way, a voltage for driving the memory cell array is lowered in accordance with the extent of miniaturization of memory cells, if the voltage is lowered for common use with other circuits, stabilization of voltage within a chip will be difficult because a load current varies heavily in a DRAM. Specifically, voltage control must be performed by the use of a large-sized transistor which can drive a large instantaneous current and moreover the large-sized transistor requires a large-sized driving amplifier consuming a large amount of power. The stabilization of the feedback loop of a control circuit is not easy. Moreover, voltages for a cell array and peripheral circuits cannot always be optimized. Furthermore, even in the case where the peripheral circuits and the sense amplifiers are driven by separate voltages that are generated within a chip, if the amplitude of the sense amplifier were lowered in accordance with a desired voltage of the cell array, the access time would be prolonged.